Daily Learning Notes for January 13, 2016

Time for more fun with computer science and NAND2Tetris! Today I hope to finally finish implementing these 15 chips for the first project!

This morning while sitting at the breakfast table with my dad and step-mom, I drew a schematic diagram for an implementation of a 4-way demultiplexer, which can be extended into an 8-way demultiplexer by making more copies of its internal building block, which looks like a pretty simple design now that I figured it out!

Well, here’s the catch: I’ve yet to test any of my designs. I may have gotten them all wrong! But I wanted to figure them out on paper and try to get them right using nothing but pen, paper and brain power before I turn to the hardware simulator.

I filmed my first look at the NAND2Tetris hardware simulator, so a record of my confusion will be probably be available on the internet until the end of time. I’m OK with that. It was fun. Now I’m finally going to take a second look at that hardware simulator and actually use it for something. Let’s simulate some chips!

Writing HDL and testing chips in the hardware simulator

Before I can test my chips, I need to create a machine-readable version of them in the specified Hardware Description Language (HDL)! Now I’m glad I took notes when I first started learning about this stuff! I reviewed my notes from January 1st and January 9th to refresh my memory.

I opened up the Not.hdl file, which came included in the free NAND2Tetris software suite. (I love that they provide a folder for each week’s project. So organized!) The file is partially completed; all I need to do is declare the parts, building everything up from primitive NAND gates, which come built-in.

The Hardware Description Language (HDL) Survivor Guide by Mark Armbrust includes an API of sorts for all the chips I’ll ever need in this course, so I kept that open in a browser tab to make sure I name the inputs and outputs correctly.

The rest of this process should just be a matter of transcribing my schematic diagrams into a list of part names, input names and output names that follow the conventions of the HDL. Then I’ll load each chip’s test script and run it, following the directions outlined in the hardware simulator tutorial (PDF).

Then I open up the generated output file and check if it’s correct. For example, the test script for my NOT gate created a file named Not.out, which contains this:

|  in   |  out  |
|   0   |   1   |
|   1   |   0   |

Time spent implementing and testing each gate:

  • NOT: 10 minutes
    • Challenges: The hardware simulator wouldn’t load my chip at first, and I didn’t see any error messages! Turns out I needed to manually resize the program to see the error message at the bottom. Then it took a while for me to find my very simple syntax error related to how I’m supposed to write constants in this HDL. But then it worked! My initial design was correct, woohoo!
  • AND: 1 minute
  • OR: 1 minute
  • XOR: 3 minutes
  • Mux: 28 min
    • Challenges: My implementation was wrong! I debugged it on paper first because I thought it would be fun. Sure enough, I had accidentally switched two of the variables, negating the wrong one. It worked on the second try. Phew!
  • DMux: 4 min
  • Not16: 4 min
  • And16: 3 min
  • Or16: 1 min
  • Mux16: 2 min
  • Or8Way: 5 min

Then I got to the 4-way 16-bit mux and got completely stuck! My implementation on paper was really just for a 4-way single-bit mux, and I didn’t realize that it would be hard to scale it up. I know how it should probably work, but I don’t know how to get it to work in HDL! I need a way to pipe a single value into a bunch of other values. Or at least I think I do. Or maybe I need to go back to the drawing board.

I assume that the only practical way to implement this 4-way 16-bit mux will be to use the larger components I’ve already built. I went about it all wrong! My gut tells me I need to use the 16-bit mux and 16-bit Or gate, and maybe some other combinations of gates. But I obviously can’t build this starting with any of the single-bit gates. Oops! Back to paper.

Finally! I got it working. So, the Mux4Way16 took me another 30 or 45 minutes to redo, but at least now I definitely have a better sense of how larger chips can fit together. My second implementation was much better than the first.

Learning summary (#TIL)

  • I implemented the 4-way and 8-way demultiplexer, completing my initial designs for all 15 chips required in the first NAND2Tetris project!
  • I wrote up my implementations in HDL and tested them in the hardware simulator, confirming that I’ve correctly implemented AND, OR, NOT, XOR, Mux, DMux, Not16, And16, Or16, Mux16, Or8way, and Mux4Way16.

Next steps

  • Finish testing the last 3 chips in the hardware simulator: Mux8Way16, DMux4Way, and DMux8Way.

Time breakdown

  • Study time: 3 hours 49 min
    • NAND2Tetris project 1: 2 hours 49 min
    • Reviewing and writing up notes: 1 hour