Today was a social day for me, so I didn’t have that much time for learning about computer science with NAND2Tetris. (I had lunch with a friend and we spent the rest of the day studying and chatting.)
But I still figured out how to implement seven more of these 15 chips! It turns out it’s actually pretty easy to design a multi-bit version of a chip once you’ve already designed the basic chip. I had to build a 16-bit version of AND, OR, and NOT gates, along with a 16-bit multiplexer. All I had to do was make 16 copies of the gates I had already designed. Piece of cake!
Then I had to implement an 8-way OR gate, and at first that really threw me for a loop. All it has to do is output 1 if any of the input bits are 1. Sounds simple, right? But I ended up with this knot of NOTs, my page covered in nested overbars that represent negation. It does not look pretty in Boolean algebra. But the cascading pattern doesn’t look frightening at all when you draw it as a schematic diagram, and that’s what saved me: random doodling! Then it became simple: a cascade of each previous output feeding into the input of the next gate, starting with two of the input bits and cascading out for each additional input bit.
The 4-way mux gate worked the same way. The interesting catch in designing this one was that I couldn’t feasibly write out its entire truth table, because it has a total of 6 inputs, which means 64 possible input combinations! So I skipped that step and used the description of the gate to generate a pretty simple Boolean expression using my intuition. It follows the same pattern I ended up with for the smallest possible mux gate, so I figured that’s a good indication that I got it right. The schematic diagram for this one is also a beautiufl cascading pattern, feeding the “select bits” into a bunch of other gates that check them against each of the other input bits, ultimately passing one of them through. I figured that to build the 16-bit version of this 4-way mux, I can just link together 16 copies of my single-bit 4-way mux. And for the 8-way mux, I use the same basic design but with more cascading pieces.
Learning summary (#TIL)
- I implemented the 16-bit NOT, AND, and OR gates, a 16-bit multiplexer, an 8-way OR gate, a 4-way mux, a 16-bit 4-way mux, and a 16-bit 8-way mux.
- I realized that multi-bit versions of gates are just many copies of the single-bit versions of those gates.
- I realized that n-way gates are essentially just cascading versions of the basic gates.
Next steps
- Implement the last four chips required for the first NAND2Tetris project.
- Write up my implementations in HDL and test them with the hardware simulator.
Time breakdown
- Study time: 2 hours 25 min
- NAND2Tetris project 1 implementations: 2 hours
- Reviewing and writing up notes: 25 min
- Video production: 1 hour
- Learn to Code LA organizing: 30 min